TY - JOUR ID - 939 TI - Design of a Low-Latency Router Based on Virtual Output Queuing and Bypass Channels for Wireless Network-on-Chip JO - Journal of Communication Engineering JA - JCE LA - en SN - 2322-4088 AU - Rad, Farhad AU - Reshadi, Midia AU - Khademzadeh, Ahmad AD - Department of Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran AD - Education and International Scientific Cooperation Department, Iran Telecommunication Research Center, Tehran, Iran Y1 - 2019 PY - 2019 VL - 8 IS - 2 SP - 179 EP - 196 KW - wireless network-on-chip KW - head-of-line blocking KW - bypass channels KW - virtual output queuing KW - low-latency routers DO - 10.22070/jce.2019.3882.1117 N2 - Wireless network-on-chip (WiNoC) is considered as a novel approach for designing future multi-core systems. In WiNoCs, wireless routers (WRs) utilize high-bandwidth wireless links to reduce the transmission delay between the long distance nodes. When the network traffic loads increase, a large number of packets will be sent into the wired and wireless links and can easily fill FIFO queues at the input ports of routers. In these conditions, head-of-line (HOL) blocking and node congestion may occur and the network communications efficiency tremendously decreases. In this study, a low-latency router was proposed, which employs virtual output queuing (VOQ) and bypass channels to eliminate the congestion of routers and improves network performance. Synthetic traffic patterns were simulated using Noxim simulator and obtained results show that considerable improvement in the latency, total energy consumption and the saturation throughput can be achieved compared to the other WiNoCs. UR - https://jce.shahed.ac.ir/article_939.html L1 - https://jce.shahed.ac.ir/article_939_69ea55cf3b1dd0b7d8a272c75c95ca24.pdf ER -