In this paper, analysis, simulation and design of a distributed amplifier (DA) with 0.13µm CMOS technology in the frequency range of 3-40 GHz is presented. Gain cell is a current reused circuit which is optimum in gain, noise figure, bandwidth and also power dissipation. To improve the noise performance in the frequency range of interest, a T-matching low pass filter LC network which is utilized at the input gate of the designed amplifier. By this means, the proposed cascaded DA shows about % 28 improvements in noise figure and 20% improvement in the gain compared with those of the other well-known configuration. To show the capability of the proposed method we also compared the figure of merit of the proposed amplifier with those obtained with the other researches and showed that this figure is around 38% higher than that of those achieved by other researchers. The figure of merit includes gain, bandwidth, power consumption and also noise figure.