Design of a Low-Latency Router Based on Virtual Output Queuing and Bypass Channels for Wireless Network-on-Chip

Rad, Farhad; Reshadi, Midia; Khademzadeh, Ahmad

doi:10.22070/jce.2019.3882.1117

Design of a Low-Latency Router Based on Virtual Output Queuing and Bypass Channels for Wireless Network-on-Chip

Document Type : Research Paper

Authors

Farhad Rad ¹

Midia Reshadi ¹

Ahmad Khademzadeh ²

¹ Department of Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran

² Education and International Scientific Cooperation Department, Iran Telecommunication Research Center, Tehran, Iran

10.22070/jce.2019.3882.1117

Abstract

Wireless network-on-chip (WiNoC) is considered as a novel
approach for designing future multi-core systems. In WiNoCs, wireless
routers (WRs) utilize high-bandwidth wireless links to reduce the
transmission delay between the long distance nodes. When the network
traffic loads increase, a large number of packets will be sent into the wired
and wireless links and can easily fill FIFO queues at the input ports of
routers. In these conditions, head-of-line (HOL) blocking and node
congestion may occur and the network communications efficiency
tremendously decreases. In this study, a low-latency router was proposed,
which employs virtual output queuing (VOQ) and bypass channels to
eliminate the congestion of routers and improves network performance.
Synthetic traffic patterns were simulated using Noxim simulator and
obtained results show that considerable improvement in the latency, total
energy consumption and the saturation throughput can be achieved
compared to the other WiNoCs.

Keywords

wireless network-on-chip

head-of-line blocking

bypass channels

virtual output queuing

low-latency routers